 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| datasheet, v1.4, 27 april 20 04 ice 1qs01 controller for quasiresonant switch mode power supplies supporting low power standby and power factor correction never stop thinking. power management & supply
edition 2004-04-27 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted char- acteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest in- fineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the fail- ure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life sup- port devices or systems are intended to be implanted in the human body, or to support and/or maintain and sus- tain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons ice1qs01 revision history: current version: 2004- 04-27 previous version: 2003- 11-28 page13 (in previous version) page 13 (in current version) diagram mains undervoltage lockout curent added page 16-18 (in previous version) page 16-18 (in current version) min.- max.- values added, typ. values adapted, according to measuring results. page 20 (in previous version) page 20 (in current version) application circuit changed to new 250 w demo board with pfc current pump. ice1qs01 version 1.4 3 27 apr 2004 controller for switch mode power supplies supporting low power standby and power factor correction (pfc) features ? quasiresonant operation ? primary and secondary regulation ? primary current simulation ? standby input power < 1 w ? low power consumption ? very low start-up current ? soft-start for noiseless start-up ? standby burst mode with and without control signal for lowered output voltages ? digital frequency reduction in small steps at decreasing load ? over- and undervoltage lockout ? switch off at mains undervoltage ? mains voltage dependent fold back point correction ? ringing suppression time controlled from output voltage ? free usable fault comparator functional description the ice1qs01 is optimized to control free running flyback converters with and without power factor correction (with pfc charge pump). the switching frequency is reduced in small steps with decreasing load towards a minimum of 20 khz in standby mode. this function is performed by a digital circuit to avoid any jitter also with periodically pulsed loads. to provide extremely low power consumption at light loads, this device can be switched into standby burst mode. this is also possible without standby control signal (for adapter application). additionally, the start up current is very low. to avoid switching stresses of the power devices, the power transistor is always switched on at minimum voltage. the device has several protection functions: v cc over- and undervoltage, mains undervoltage and current limiting. regulation can be done by using the internal error amplifier or an opto coupler feedback. the output driver is ideally suited for driving a power mosfet. the ice1qs01 is suited for tv-sets, dvd- sets, sat- receivers and other consumer applications in the power range from 0 to app. 300 w. type ordering code package ice1qs01 q67040-s4558 p-dip-8 ICE1QS01G q67040-s4559 p-dso-8 p-dip-8-4 p-dip-8-4 p-dso-8-3 p-dso-8-3 ice1qs01 version 1.4 4 27 apr 2004 block diagram rzi uvlo q q set clr s r reference voltage and current gnd out power driver ringing suppression time 1v 50mv ofc pcs src vcc 1v 2v burst-mode + - + - + - + - + - + - + - 3.5v 4.5v + - 4.8v + - 20v overvoltage protection start digital processing 50s timer 50ms timer zc-counter up/do-counter latch primary regulation + - 5v q q set clr d l 1v + - foldback point corr. 1.5v + - 5.7v 5v 5v 20k ice1qs01 version 1.4 5 27 apr 2004 pinning pin configuration (top view) pin symbol function 1n.c. 2 pcs primary current simulation 3 rzi regulation and zero crossing input 4 src soft-start and regulation capacitor 5 ofc overvoltage fault comparator 6 gnd ground 7 out output 8 vcc supply voltage 1 2 3 45 6 7 8 n.c. pcs rzi src vcc out gnd ofc 8 7 6 5 1 2 3 4 pcs rzi src vcc out gnd ofc ice1qs01 version 1.4 6 27 apr 2004 functional description start up an internal start up diode is connected between pin pcs and pin v cc . start up current is provided via this diode if v pcs is higher than v cc + v be (v be = base-emitter-voltage). during start up the internal reference of the ic is shut off and current consumption is about 60 a. there is only the start up circuitry working which determines the v ccon threshold. gate driver out is switched to low. an active shut down circuitry ensures that out is held below the mos gate threshold when the ic is in start up mode. block diagram: start up pcs uvlo ice1qs01 vcc out ice1qs01 version 1.4 7 27 apr 2004 soft start the internal reference of the ic is switched on when v cc exceeds the v ccon threshold. the ic begins to work with soft start mode. soft start is realized with an internal soft start resistor, an inter- nal current sink, a current source and the external feedback capacitor connected at pin src. the internal resistor is connected between the internal voltage reference and pin src. the current sink is connected between pin src and gnd. the value of the current is set with a timer. immediately after the ic is switched on the capacitor c src is charged with a current source up to 2.5v. this cur- rent source is switched off 12 sec after beginning of soft start. the current value of the current sink is set with a timer. every three msec the current of the current sink is reduced and so v src can increase stepwise. the soft start is finished 24 msec after the ic is switched on. at the end of the soft start the current sink is switched off. figure: soft start pcs (primary current simulation) a voltage proportional to the current of the power transistor is generated at pin pcs by the rc-com- bination r2, c2. the voltage at pin pcs i s for ced to 1.5v when the power transistor i s switched off and during its switch on time c2 is charged by r2 from the rectified mains. the rela tion of v pcs and ton tp1 tp2 vccon vsrc1 vsrc2 vsrc vcc t t 20k pin src current sink up down counter d/a timer tp=3ms 2.5v ice1qs01 timer t=12us 500 5v timer t=24ms ice1qs01 version 1.4 8 27 apr 2004 the current in the power transistor (iprimary) is: lprimary: primary inductance of the transformer the advantage of primary current simulation is the elimination of the leading edge spike, which is generated when the power transistor is switched on. rzi (zero crossing input and primary regulation) zero current counter every time when the falling voltage ramp of v rzi crosses the 50 mv threshold a pulse is sent to the zero-current-counter and increases the counter by one. if zero-current-counter and up-down-coun- ter are equal the gate drive out is switched to high. up-down counter is influenced via src voltage as described below. if v rzi is greater than 50 mv gate drive out is always switched low. figure: zero crossing switching behaviour vpcs 15 v , 2 c 2 ------------------------------------------------------- - + = vrzi out ton tof f ton toff vpcs vsrc v t t t status up- down counter = 0001: switch on at first zero crossing status up- down counter = 0010: switch on at second zero crossing 1.5v ice1qs01 version 1.4 9 27 apr 2004 ringing suppression when v pcs reaches the feedback voltage v src the gate drive out is set to low and the ringing suppression timer is started. this timer ensures that the gate drive cannot be switched on until this ringing suppression time is passed. duration of ringing suppression time depends on the v rzi volt- age. suppression time is 3 sec if v rzi > 1v and it is 30 sec if v rzi < 1v. figure: ringing suppression vrzi out ringing suppression time 1v 30 us 3 s up-down-counter =1 up-down-counter =1 vsrc vpcs 1.5v ice1qs01 version 1.4 10 27 apr 2004 primary regulation primary regulation is achieved by activating the internal current sink. the current sink is connected between pin src and ground. if v rzi exceeds the 5v threshold the current sink is switched on. it is switched off when v rzi falls below 5v. the current sink discharges the c src capacitor. c src is charged via the internal 20k resistor. if v rzi exceeds the 4.4v threshold a flip-flop is set and the resistor is switched off when v rzi falls below 50 mv. the resistor is switched on again with the fall- ing slope of gate drive out. diagram primary regulation rzi src 5v 20k + - 5 v current sink ice1qs01 4.5 v 0.05 v + - - + r s q q r s q q r s q q out start stop vrzi 5v out 4.5v 20k resistor current sink vsrc zero current counter = 0010 t on off on off ice1qs01 version 1.4 11 27 apr 2004 src (regulation and soft start capacitor) the feedback capacitor is connected to pin src. the feedback voltage v src has two main func- tions. function i (mos fet on time): v src provides the switch off reference voltage. if v pcs (which con- tains the primary current information) exceeds the v src voltage the external mos transistor is switched off. function ii (mos fet off time for frequency reduction): at low load the frequency is reduced by ignoring zero crossing signals after the transformer demagnetization. v src determines the action of the 4-bit up-down-counter which contains the number of zero crossings to be ignored. the content of the up-down-counter is compared with t he number of zero-current crossings of v rzi. if the number of zero-current crossings in each period after the transformer demagnetization is equal to the up-down-counter content the mos is switched on. at low load conditions when v src is below 3.5v the counter is increased by one every 50 msec. the result is that the mos transistor off-time increases and duty cycle decreases. at high load conditions when v src is higher than 4.4v the counter content is reduced by one every 50msec. so mos transistor off-time will be reduced. with this off-time regulation switching jitter can be eliminated. the up-down-counter is immediately set to 0001 if a load jump occurs and v src exceeds 4.8 v. this ensures that full power can be provided instantaneously. the following table shows the src voltage range and the corresponding up-down counter action. the information provided by v src is stored in two independent flip flops. an internal timer creates a trigger pulse with a period of 50 msec. every time the pulse occures the up-down counter checks the status flip flops and acts depending on the flip flop information. after this pulse the flip flops are reset. so change of voltage range is noticed by the logic only once during the 50 ms period. in the diagram below the behaviour of the up- down counter is depicted in more detail. src voltage range up-down-counter action 1: vsrc< 3.5v count forward 2: 3.5 ice1qs01 version 1.4 12 27 apr 2004 burst mode 12 sec after beginning of softstart the burst mode comparator is activated. if v src falls below 2v after activating the comparator the gate drive out is switched to low and the v ccoff threshold is changed to 14.5 v. v cc decreases because gate drive is held low. if v cc reaches the v ccoff thresh- old the ic is going into start-up mode. at v ccon threshold the ic is switched on again starting with soft start modus. v ccoff threshold is set to the normal 9v. figure: burst mode out vcc 15v 14.5v 9v soft start v src 2v vsec normal mode burst mode secondary load high low t vccoff ice1qs01 version 1.4 13 27 apr 2004 restart timer if voltage v rzi is lower than 50 mv and gate drive out is low an internally created restart pulse will switch gate drive out high every 50 s and the minimum switching frequency is about 20 khz. restart pulse is inhibited if v rzi is higher than 50 mv. so the mos transistor cannot be switched on until the transformer is discharged. vcc overvoltage protection if v cc exceeds the v ccd threshold a latch is set and the gate is disabled. reset of latch occurs when v cc is falling below v ccon - v ccbhy. overvoltage fault comparator (ofc) with an external sense resistor connected to pin ofc primary current can be sensed directly. if the sensed current exceeds the internal v ofc threshold a latch is set and gate is disabled. reset of latch occurs when v cc is falling below v ccon - v ccbhy . notice: if this comparator is not used pin ofc has to be connected to ground. mains undervoltage power supplies must be shut down when mains voltage is below a certain limit to avoid too long on- time of mos-fet switch, which would lead to a switching frequency in audible spheres. mains und- ervoltage is sensed during the off-time of the mos-fet switch. if the current flowing into pin pcs is smaller than 100 ua, then the output is latched and cannot be switched to high state. diagram mains undervoltage lockout current temp./c ipcs/a 50 60 70 80 90 100 110 120 130 -40 -30 -20-10 0 1020304050 60 70 80 90 100 110 120 130 140 150 ice1qs01 version 1.4 14 27 apr 2004 fold back point correction with increasing mains voltage the switch on time becomes shorter and so the frequency becomes higher. with higher frequency also the maximal possible output power becomes higher. with higher power the danger in case of failure increases. to avoid this, the foldback point correction circuit senses main voltage to reduce the on-time of the switch. mains voltage is sensed at the supply coil of v cc voltage via a resistor connected to pin rzi. during on-time of the mos-fet switch current is pulled out from pin rzi. when this current is higher than 500 a, one fifth of the current higher than this threshold is driven into pin pcs to increase the voltage slope charging the capacitor connected to this pin. figure: fold back point correction ipcsfo irzi 0 ?5 ma , 5 -------------------------------- - irzi 500 ua > () , = 5v vpcs with fold back point correction vpcs at low mains voltage vpcs at high mains voltage t0 t1 t2 t3 t vpcs pmax without fold back point correction pmax with fold back point correction vmains pmax ice1qs01 version 1.4 15 27 apr 2004 abso l ute maximum ratings parameter symbol min max unit remark charge current into pin2 i pcs 500 ua during start up voltage at pin 2 v pcs -0.3 21 v current into pin 3 i rzi i rzi -10 10 ma ma v rzi >v rzich v rzi ice1qs01 version 1.4 17 27 apr 2004 rzi (regulation and zero crossing input) zero crossing threshold voltage v rzit1 25 50 80 mv v rzi ice1qs01 version 1.4 19 27 apr 2004 figure: cir cuit diagr am for standar d application with pfc ice1qs01 version 1.4 20 27 apr 2004 figure: circuit diagram for application with pfc and low voltage standby mode ice1qs01 version 1.4 21 27 apr 2004 gps05121 plastic package, p-dso-8-3 (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm smd = surface mounted device plastic package, p-dip-8-4 (plastic dual in-line package) gpd05025 |
Price & Availability of ICE1QS01G
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |